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GMS81504 cmos single-chip 8-bit microcontroller overview development tools the gms800 family is supported by a full-featured macro assembler, an in-circuit emulators choice- jr. tm , socket adapters for otp device. the availability of otp devices are especially useful for customers expecting frequent code changes and updates. the otp devices, packaged in plastic pack - ages permit the user to program them once. in addition to the program memory, the configuration fuses must be programmed. in-circuit emulators choice-jr. tm otp devices GMS81504t k (30 sdip) socket adapters for otp devices oa815a-30sd (30 sdip) assembler h m e macro assembler 4k on-chip program memory 128 bytes of on-chip data ram instruction execution time: 0.5us at 8mhz 2.7v to 5.5v wide operating range 1~8 mhz operating frequency basic interval timer two 8-bit timer/ counters (can be used as one 16-bit) two external interrupt ports one programmable clock out port one buzzer driving port 23 programmable i/o lines seven interrupt sources all led direct drive output ports 4-channel 8-bit on-chip analog to digital converter power down mode (stop mode) description the GMS81504 is a high-performance cmos 8-bit microcontroller with 4k bytes of rom. the de v ice is one of gms800 family. the hyundai GMS81504 is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. the GMS81504 provide s the following standard features: 4k bytes of rom, 128 bytes of ram, 23 i/o lines(21 lines for 28sop), 16-bit o r 8-bit timer/counter, a precision analog to digital converter, on-chip oscillator and clock circu itry. in addition, the GMS81504 supports power saving modes to reduce power consumption. the stop mode saves the ra m contents but freezes the oscillator disabling all other chip functions until the next hardware rese t or external interrupt. feature s rom size ram size package device name 4k bytes 128 bytes 30sdip GMS81504 k 28sop GMS81504 d 4k bytes (otp) 128 bytes 30sdip GMS81504t k h y un da i m i croelectronics GMS81504 1
block diagram timer 0 cpu timer 1 bit* adc ext int buzzer rom 4k x 8 ram 128 x 8 port 4 port 5 port 0 port 6 r00~r07 i/o r40~r47 i/o r64 r65 r66 r67 * bit: basic interval timer ** the r56, r57 port are not served on 28sop package. r55/buz r56** r57** 8 8 figure 1. block diagram GMS81504 hyundai microelectronics 2
pin assignment 30 sdip 28 sop figure 2. pin connections hyundai microelectronics GMS81504 3
packages 30 sdip 28 sop unit: inch 0.106 0.093 0.713 0.697 0.020 0.013 0.050 bsc 0.0118 0.004 0.042 0.016 0.0125 0.008 0.299 0.292 0.419 0.398 0 ~8 GMS81504 hyundai microelectronics 4
pin descriptions v dd : supply voltage. v ss : circuit ground. test : for test purposes only. connect it to v dd . reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal clock operating circuit. x out : output from the inverting oscillator amplifier. r00~r07 : r0 is an 8-bit, cmos, bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. r0 pins that have 1 or 0 written to their port direction mode register, can be used as outputs or inputs. r40~r47 : r4 is an 8-bit, cmos, bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. r4 pins that have 1 or 0 written to their port direction mode register, can be used as outputs or inputs. in addition, port r40, r41, r44, r46 serve the func - tions of the various following special features. port pin alternate function r40 int0 (external interrupt 0) r41 int1 (external interrupt 1) r44/ ec0 ec0 (external count input to timer/counter 0) r46 t1o (timer 1 clock-out) r55, r56, r57 : r5 is a 3-bit, cmos, bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. r5 pins that have 1 or 0 written to their port direction mode register, can be used as outputs or inputs. r56 and r57 differs in having internal pull-ups. port r55 serves the functions of special features. port pin alternate function r55 buz (square wave output for buzzer driving) r64~r67 : r6 is an 4-bit, cmos, bidirectional i/o port. r64~r67 are bidirectional i/o port. as an output port each pin can sink several ls ttl inputs. r64~r67 pins that have 1 or 0 written to their port direction mode register, can be used as outputs or inputs. r6 serves the analog to digital converter functions of following. port pin alternate function r64 r65 r66 r67 an4 (adc input 4) an5 (adc input 5) an6 (adc input 6) an7 (adc input 7) av dd : supply voltage to the ladder resistor of adc circuit. to enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. hyundai microelectronics GMS81504 5
port pin i/o descriptions pull-up/ pull-down reset stop mode primary functions secondary functions v dd - power supply to mcu - - - - v ss - ground - - - - av dd - power supply for adc - - - - test i test mode - - - - reset i reset the mcu - pull-up low last state x in i oscillation input - - oscillation low x out o oscillation output - - oscillation high r00~r07 i/o general i/o - - input 3) last state r40/int0 r41/int1 r42 r43 r44/ ec0 r45 r46/t1o r47 i/o i/o i/o i/o i/o i/o i/o i/o general i/o " " " " " " " external interrupt 0 external interrupt 1 - - external count input 0 - timer 1 output - - input 3) last state r55/buz r56 1) r57 1) i/o i/o i/o general i/o " " buzzer driving output - - - pull-up 2) pull-up 2) input 3) last state r64/an4 r65/an5 r66/an6 r67/an7 i/o i/o i/o i/o general i/o " " " analog input 4 analog input 5 analog input 6 analog input 7 - input 3) last state notes: 1) r56 and r57 are not physically served on 28 pin sop package. 2) when input mode is selected, pull-up is activated. in output mode, pull-up is de-activated . 3) during mcu reset, status of r56,r57 are weak high (typ. impedance 50~100k w ). other pin impedance is very high(high-z). GMS81504 hyundai microelectronics 6
port structures data bus data bus data bus mux rd. protect diode protect diode v ss v dd direction reg. data reg. r00~r07, r47 data bus data bus data bus pmr4 alternate function ex) int0 rd. mux data reg. direction reg. r40/int0, r41/int1, r44/ ec0 data bus data bus selection (pmr) alternate function ex) t1o direction reg. rd. data reg. data bus mux mux r46/t1o, r55/buz hyundai microelectronics GMS81504 7
data reg. direction reg. rd. mux data bus data bus data bus to a/d converter ch. select rd. 0: output 1: reset, input, ad ch. select r64/an4, r65/an5, r66/an6, r67/an7 data reg. direction reg. rd. mux data bus data bus data bus pull-up resistor input mode: pull-up resistor is activated. output mode: pull-up resistor is de-activated. r56, r57 data bus data bus data bus mux rd. protect diode protect diode v ss v dd direction reg. data reg. r42, r43, r45 GMS81504 hyundai microelectronics 8
pull-up resister reset otp: no p-ch diode test x in x out stop v dd v dd v dd x in , x out hyundai microelectronics GMS81504 9
electrical characteristics absolute maximum ratings recommended operating conditions parameter symbol condition specifications unit min. max. supply voltage v dd f xin = 8 mhz f xin = 4 mhz 4.5 2.7 5.5 5.5 v operating frequency f xin v dd = 4.5~5.5v v dd = 2.7~5.5v 1.0 1.0 8.0 4.2 mhz operating temperature t opr -20 80 c supply voltage . . . . . . . . . . . . . . . -0.3 to +6.0 v storage temperature . . . . . . . . . . . . -40 to +125 c voltage on any pin with respect to ground (v ss ) . . . . . . -0.3 to v dd +0.3 v maximum current out of v ss pin . . . . . . . . . 150 ma maximum current into v dd pin . . . . . . . . . 100 ma maximum output current sunk by (i ol per i/o pin) r00~r07, r42, r43, r56, r57 . . . . . . . . 30 ma r40, r41, r44~r47, r55, r64~67 . . . . . . 20 ma maximum output current sourced by (i oh per i/o pin) r00~r07, r42, r43, r56, r57 . . . . . . . . 24 ma r40, r41, r44~r47, r55, r64~67 . . . . . . 18 ma maximum current ( s i ol ) . . . . . . . . . . . . 120 ma maximum current ( s i oh ) . . . . . . . . . . . . 100 ma notice: stresses above those listed under "absolute maxi - mum ratings" may cause permanent damage to the device. this is a stress rating only and func - tional operation of the device at these of any other conditions above those indicated in the op - erational sections of this specification is not im - plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. GMS81504 hyundai microelectronics 10
dc characteristics ( 5v ) (v dd = 5.0v 10%, v ss = 0v, t a = -20 ~ 80 c, f xin = 8 mhz) parameter pin symbol test condition specifications unit min. typ.* max. input high voltage x in v ih1 - 0.9v dd - v dd v reset , r0, r4, r5, r6 v ih2 - 0.8v dd - v dd v input low voltage x in v il1 - 0 - 0.1v dd v reset , r0, r4, r5, r6 v il2 - 0 - 0.2v dd v output high voltage r0, r4, r5, r6 v oh v dd = 5v i oh = -2ma v dd -1. 0 v dd -0.2 - v output low voltage r40, r41, r44~r47, r55, r6 v ol1 v dd = 5v i ol = 5ma - 0.3 1.0 v r0, r42, r43, r56, r57 v ol2 v dd = 5v i ol = 10ma - 0.6 1.0 v input leakage current reset , r0, r4, r5, r6 i ih v i = v dd -5.0 - 5.0 ua i il v i = 0v -5.0 - 5.0 ua input pull-up current reset i p1 v dd = 5v -180 -120 -30 ua r56, r57 i p2 v dd = 5v -90 -60 -15 ua power current operating mode i dd f xin =8mhz - 5 40 ma stop mode i stop v dd = 5v - 2 30 ua hysteresis reset , r40~r45 v t + ~v t - v dd = 5v 0.5 0.8 - v * : data in "typ" column is at 5 v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. a/d converter characteristics ( 5v ) (v dd = 5.0v 10%, v ain = 5.0v, v ss = 0v, t a = 25 c ) parameter symbol specifications unit min. typ.* max. analog input range v ain v ss - av dd v overall accuracy a cc - 2.0 3.0 lsb conversion time t conv - - 40 us analog power supply input range v avdd 4.5 5.0 5.5 v * : data in "typ" column is at 5 v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. hyundai microelectronics GMS81504 11
dc characteristics ( 3v ) (v dd = 3.0v 10%, v ss = 0v, t a = -20 ~ 80 c, f xin = 4 mhz) parameter pin symbol test condition specifications unit min. typ.* max. input high voltage x in v ih1 - 0.9v dd - v dd v reset , r0, r4, r5, r6 v ih2 - 0.8v dd - v dd v input low voltage x in v il1 - 0 - 0.1v dd v reset , r0, r4, r5, r6 v il2 - 0 - 0.2v dd v output high voltage r0, r4, r5, r6 v oh v dd = 3v i oh = -2ma v dd -1. 0 v dd -0.4 - v output low voltage r40, r41, r44~r47, r55, r6 v ol1 v dd = 3v i ol =2ma - 0.3 1.0 v r0, r42, r43, r56, r57 v ol2 v dd = 3v i ol = 5ma 0.4 1.0 v input leakage current reset , r0, r4, r5, r6 i ih v i = v dd -3.0 - 3.0 ua i il v i = 0v -3.0 - 3.0 ua input pull-up current reset i p1 v dd = 3v -15 -30 -60 ua r56, r57 i p2 v dd = 3v -7.5 -15 -30 ua power current operating mode i dd f xin =4mhz - 1 5 ma stop mode i stop v dd = 3v - 1 10 ua hysteresis reset , r40~r45 v t + ~v t - v dd = 3v 0.3 0.6 - v * : data in "typ" column is at 3 v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. **: power fail detection function is not available. a/d converter characteristics ( 3v ) (v dd = 3.0v 10%, v ain = 3.0v, v ss = 0v, t a = 25 c) parameter symbol specifications unit min. typ.* max. analog input range v ain v ss - av dd v overall accuracy a cc - 1.5 2.5 lsb conversion time t conv - - 40 us analog power supply input range v avdd 2.7 3.0 3.3 v * : data in "typ" column is at 3 v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. GMS81504 hyundai microelectronics 12
ac characteristics (v dd = 2.7~5.5v, v ss = 0v, t a = -20 ~ 80 c) parameter pin symbol specifications unit min. typ. max. main clock frequency x in f xin 1 - 8 mhz oscillation stabilization time x in , x out t st 20 - - ms external clock pulse width x in t cpw 80 - - ns external clock transition time x in t rcp , t fcp - - 20 ns interrupt pulse width int0, int1 t iw 2 - - t sys reset input low width reset t rst 8 - - t sys event counter input pulse width ec0 t ecw 2 - - t sys event counter transition time ec0 t rec , t fec - - 20 ns x in 1 / f osc t rcp t fcp t cpw t cpw 0.1v dd 0.9v dd t iw 0.8v dd 0.2v dd t iw int0, int1 reset t rst 0.2v dd ec0 t rec t fec t ecw t ecw 0.8v dd 0.2v dd timing chart hyundai microelectronics GMS81504 13
typical characteristics these parameters are for design guidance only and are not tested. 1 2 3 4 0 i ol - v ol r00~r07, r42, r43, r56, r57 6 12 18 24 i ol (ma) v dd =5.0v t a =25 c v ol (v) v dd =5v 1 2 3 4 0 i ol - v ol 5 10 15 20 i ol (ma) r40, r41, r44~r47, r55, r64~67 v ol (v) v dd =5.0v t a =25 c 1 2 3 4 0 i oh - v oh -5 -10 -15 -20 i oh (ma) v dd =5.0v t a =25 c r40, r41, r44~r47, r55, r64~67 v dd -v oh (v) 1 2 3 4 0 i oh - v oh -6 -12 -18 -24 i oh (ma) v dd -v oh (v) v dd =5.0v t a =25 c r00~r07, r42, r43, r56, r57 2 3 4 5 0 i dd - v dd 2 4 6 8 i dd (ma) t a =25 c v dd (v) f xin = 4mhz f xin = 8mhz 2 3 4 5 0 i stop 2 4 6 8 i stop (ua) t a =25 c v dd (v) GMS81504 hyundai microelectronics 14
0.5 1.0 1.5 2.0 0 2.5 (v) i ol - v ol r00~r07, r42, r43, r56, r57 5 10 15 20 i ol (ma) v dd =3.0v t a =25 c v ol v dd =3.0v 0.5 1.0 1.5 2.0 0 2.5 (v) i ol - v ol 2 4 6 8 i ol (ma) r40, r41, r44~r47, r55, r64~67 v ol v dd =3.0v t a =25 c 0.5 1.0 1.5 2.0 0 2.5 (v) i oh - v oh -2 -4 -6 -8 i oh (ma) v dd ---- v oh v dd =3.0v t a =25 c r40, r41, r44~r47, r55, r64~67 0.5 1.0 1.5 2.0 0 2.5 (v) i oh - v oh -2 -4 -6 -8 i oh (ma) v dd ---- v oh v dd =3.0v t a =25 c r00~r07, r42, r43, r56, r57 hyundai microelectronics GMS81504 15
memory organization the GMS81504 has separate address spaces for pro - gram and data memory. program memory can only be read, not written to. it can be up to 4k bytes of program memory. data memory can be read and written to up to 128 bytes including the stack area. registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x,y), the stack pointer (sp) and the program status word (psw). the program counter consists of 16-bit register. accumulator : the accumulator is the 8-bit general purpose register, used for data operation such as trans - fer, temporary saving and conditional judgment, etc. the accumulator can be used as a 16-bit register with y register as shown below. x register, y register : in the addressing modes which use these index registers, the register contents are added to the specified address and this becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have increment, decrement, compare and data transfer functions and they can be used as simple accumulators. stack pointer : the stack pointer is an 8-bit register used for occurrence interrupts and calling out subrou - tines. the stack can be located at any position within 00 h to 7f h of the internal data memory. caution: the stack pointer must be initialized by software because its value is undefined after reset. ex ) ldx #07fh txsp ; sp ? 7f h caution: to prevent overrapped between user ram an sys - tem stack area, user have to consider using ram. reset routine example: org 0f000h reset: ldx #0 lda #0 clr_lp: sta {x}+ ;ram clear cmpx #80h bne clr_lp ldx #07fh ;initialize sp. txsp : program counter: the program counter is a 16-bit wide which consists of two 8-bit registers, pch, pcl. this counter indicates the address of the next instruc - tion to be executed. in reset state, the program counter has reset vector address (pch: ff h , pcl: fe h ). . program status word : the program status word (psw) contains several status bits that reflect the cur - rent state of the cpu. the psw shown in figure 6. it contains the negative flag, the overflow flag, the direct page flag, the break flag, the half carry (for bcd operations), the interrupt enable flag, the zero pch pcl a x sp y psw accumulator program counter x register y register stack pointer program status word figure 3. configuration of registers y a y a two 8-bit registers one "ya" 16-bit register figure 4. configuration of ya 16-bit register 0 sp hardware fixed. 15 8 7 0 stack address (00 h ~7f h ) figure 5. stack pointer GMS81504 hyundai microelectronics 16
flag and the carry bit. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic opera - tion or data transfer is "0" and is cleared by any other result. [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all interrupts are disabled when cleared to "0". this flag immediately becomes "0" when an interrupt is served. it is set by the ei instruc - tion, cleared by the di instruction. [half carry flag h] after operation, set when there is a carry from bit 3 of alu or there is not a borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction, clearing with overflow flag (v). [break flag b] this flag set by software brk instruction to distin - guish brk from tcall instruction which as the same vector address. [direct page flag g] this flag is not available on GMS81504 because this flag is usable over 256 bytes ram other than the GMS81504, assign direct page for direct addressing mode. in the direct addressing mode, addressing area is within zero page 00 h to ff h when this flag is "0". if it is set to "1", addressing area is 100 h to 1ff h . it is set by setg instruction, and cleared by clrg. [overflow flag v] this flag is set to "1" when an overflow occurs in the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction exceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, for other than the above, bit 6 of memory is copy to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. when the bit instruction is executed, bit 7 of memory is copy to this flag. n carry flag receives carry out v g b h i z c zero flag interrupt enable flag half carry flag receives carry out from bit 1 of addition operands brk flag g flag to select direct page (not available on GMS81504) overflow flag negative flag psw msb lsb reset value: 00h figure 6. psw (program status word) register hyundai microelectronics GMS81504 17
m(sp) ? (pch) 1) interrupt sp ? sp - 1 m(sp) ? (pcl) sp ? sp - 1 m(sp) ? (psw) sp ? sp - 1 (pch) ? m(sp) 2) reti sp ? sp + 1 (pcl) ? m(sp) sp ? sp + 1 (psw) ? m(sp) sp ? sp + 1 m(sp) ? (pch) 3) call sp ? sp - 1 m(sp) ? (pcl) sp ? sp - 1 4) ret sp ? sp + 1 (pch) ? m(sp) sp ? sp + 1 (pcl) ? m(sp) m(sp) ? acc. 5) push a (x,y,psw) sp ? sp - 1 m(sp) ? (pch) 6) pop a (x,y,psw) sp ? sp + 1 figure 7. stack operation GMS81504 hyundai microelectronics 18
program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this devices have 4k bytes (8k for gms81608) program memory space only the physi - cally implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8, shows a map of the upper part of the program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h , ffff h . as shown in figure 8, each area is assigned a fixed location in program memory. program memory area contains the user program, page call (pcall) area contains subroutine program, to reduce program byte length because of using by 2 bytes pcall instead of 3 bytes call instruction. if it is frequently called, more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences execution of the service routine. the table call service locations are spaced at 2-byte interval : ffc0 h for tcall15, ffc2 h for tcall14, etc. address tcall name ffc0 h ffc2 h ffc4 h ffc6 h ffc8 h ffca h ffcc h ffce h ffd0 h ffd2 h ffd4 h ffd6 h ffd8 h ffda h ffdc h ffde h tcall15 tcall14 tcall13 tcall12 tcall11 tcall10 tcall9 tcall8 tcall7 tcall6 tcall5 tcall4 tcall3 tcall2 tcall1 tcall0/ brk 1) 1) the brk software interrupt is using same address with tcall0. the interrupt causes the cpu to jump to specific location, where it commences execution of the service routine. the external interrupt 0, for example, is as - signed to location fffa h . the interrupt service loca - tions are spaced at 2-byte interval : fff8 h for external interrupt 1, fffa h for external interrupt 0, etc. any area from ff00 h to ffff h , if it not going to be used, its service location is available as general pur - pose program memory. address vector name ffe0h ffe2h ffe4h ffe6h ffe8h ffeah ffech ffeeh fff0h fff2h fff4h fff6h fff8h fffah fffch fffeh - - - basic interval timer - analog to digital converter - - timer/ counter 1 timer/ counter 0 - - external interrupt 1 external interrupt 0 - reset f000h ffffh feffh ff00h program memory pcall area ffbfh ffc0h tcall area interrupt vector area ffdfh ffe0h figure 8. program memory hyundai microelectronics GMS81504 19
data memory figure 9 shows the internal data memory space avail - able. data memory are divided into three groups, a user ram, control registers and stack. the stack pointer should be initialized within 00 h to 7f h by software because of implemented area of internal data memory. the control registers are used by the cpu and periph - eral functions for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters, i/o ports. the control registers are in address c0 h to ff h . note that unoccupied addresses may not be imple - mented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. more detail informations of each register are explained in each peripheral sections. caution: write only registers can not be accessed by bit manipulation instruction. address symbol r/w power-on reset value msb lsb c0h c1h c8h c9h cah cbh cch cdh d0h d1h d3h 2) d3h 2) e2h e4h e5h e8h e9h ech f4h f5h f6h f7h f8h r0 r0dd r4 r4dd r5 r5dd r6 r6dd pmr4 pmr5 bitr ckctlr tm0 + note 3 + note 3 adcm adr bur ienl irql ienh irqh ieds r/w w 1) r/w w 1) r/w w 1) r/w w 1) w 1) w 1) r w 1) r/w r/w r/w r/w 4) r w 1) r/w r/w r/w r/w w 1) x 00000000 x 00000000 x 000----- x 0000---- -0-0--00 --0----- 00000000 ---10111 00000000 x x --000001 x x 0-0----- 0-0----- 00--00-- 00--00-- 00000000 legend - = unimplemented locations. x= undefined value. notes: 1) the all write only registers can not be accessed by bit manipulation instruction. 2) the register bitr and ckctlr are located at same address. address d3h is read as bitr, as written to ckctlr. 3) several names are given at same address. refer to below table. address when read when write timer mode capture mode e4h e5h t0 t1 cdr0 cdr1 tdr0 tdr1 4) only bit 0 of adcm can be read. data memory (ram) not used 7f h 80 h 00 h 128 bytes (include stack area) control registers bf h c0 h ff h figure 9. data memory GMS81504 hyundai microelectronics 20
control registers for the GMS81504 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c0 h r0 r0 port data register c1 h r0dd r0 port direction register c8 h r4 r4 port data register c9 h r4dd r4 port direction register ca h r5 r5 port data register cb h r5dd r5 port direction register cc h r6 r6 port data register cd h r6dd r6 port direction register d0 h pmr4 - t1s - ec0s - - int1s int0s d1 h pmr5 - - buzs - - - - - d3 h 1) bitr basic interval timer data register d3 h 1) ckctlr - - - enpck btcl bts2 bts1 bts0 e2 h tm0 cap0 t1st t1sl1 t1sl0 t0st t0cn t0sl1 t0sl0 e4 h t0/ tdr0/ cdr0 timer 0 register/ timer data register 0/ capture data register 0 e5 h t1/ tdr1/ cdr1 timer 1 register/ timer data register 1/ capture data register 1 e8 h adcm - - aden ads2 ads1 ads0 adst adsf e9 h adr adc result data register ec h bur buck1 buck0 bu5 bu4 bu3 bu2 bu1 bu0 f4 h ienl ae - bite - - - - - f5 h irql aif - bitif - - - - - f6 h ienh int0e int1e - - t0e t1e - - f7 h irqh int0if int1if - - t0if t1if - - f8 h ieds - - - - ied1h ied1l ied0h ied0l legend - = unimplemented locations. notes: 1) the register bitr and ckctlr are located at same address. address d3 h is read as bitr, written to ckctlr. hyundai microelectronics GMS81504 21
i/o ports the GMS81504/08 have five ports, r0, r1, r4, r5, r6. these ports pins may be multiplexed with an alternate function for the peripheral features on the device. in general, when a initial reset state, all ports are used as a general purpose input port. all pins have data direction registers which can con - figure these pins as output or input. a "1" in the port direction register configures the corresponding port pin as output. conversely, write "0" to the corresponding bit to specify as an input pin. for example, to use the even numbered bit of r1 as output ports and the odd numbered bits as input ports, write "55 h " to address c1 h (r0 direction register) during initial setting as shown in figure 10. reading data register reads the status of the pins whereas writing to it will write to the port latch. r0 and r0dd registers: r0 is a 8-bit bidirectional i/o port (address c0 h ). each pin is individually con - figurable as input and output through the r0dd regis - ter (address c1 h ). r4 and r4dd registers: r4 is an 8-bit bidirectional i/o port (address c8 h ). each pin is individually con - figurable as input and output through the r4dd regis - ter (address c9 h ). in addition, port r4 is multiplexed with various special features. the control register pmr4 (address d0 h ) controls to select alternate function. after reset, this value is "0", port may be used as general i/o ports. to select alternate function such as external interrupt or external counter or timer clock out, write "1" to the corresponding bit of pmr4. port pin alternate function r40 r41 int0 (external interrupt 0) int1 (external interrupt 1) r44 ec0 (external count input to timer/ counter 0) r46 t1o (timer 1 clock-out) regardless of the direction register r4dd, pmr4 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. 0 1 0 1 0 1 0 1 i i o i o i o o write "55 h " to port r0 direction register 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 port r0 data r0 direction r4 data r4 direction c0h c1h : c8h i: input port o: output port c9h : figure 10. example port i/o assignment r07 r06 r05 r04 r03 r02 r01 r00 port 0 data register address: c0 h reset value: undefined r07 r06 r05 r04 r03 r02 r01 r0 0 r0dd address: c1 h reset value: 00000000 direction select 0: input 1: output input/ output data r0 port 0 direction register r47 r46 r45 r44 r43 r42 r41 r40 port 4 data register address: c8 h reset value: undefined r47 r46 r45 r44 r43 r42 r41 r4 0 r4dd address: c9 h reset value: 00000000 direction select 0: input 1: output input/ output data r4 port 4 direction register GMS81504 hyundai microelectronics 22
r5 and r5dd registers: r5 is a 3-bit bidirectional i/o port (address ca h ). r55, r56 and r57 only are physically implemented on this device. r56, r57 have internal pullups which is activated on input but deactivated on output. as input, these pins that are externally pull low will source current (i p2 on the dc characteristics) because of the internal pullups. caution: pins r56, r57 are served on 30sdip package only, but not served on 28sop . refer to pin assignment. each pin is individually configurable as input and output through the r5dd register (address cb h ). port pin alternate function r55 buz (square-wave output for buzzer driving) the control register pmr5 (address d1 h ) controls the selection alternate function. after reset, this value is "0", port may be used as general i/o ports. to use buzzer function, write "1" to the pmr5. - - r55 - - - r51 r50 port 5 data register - - r55 - - - r51 r5 0 r5dd address: cb h reset value: --0---00 direction select 0: input 1: output input/ output data r5 port 5 direction register - - buzs - - - - - pmr5 address: d1 h reset value: --0----- port 5 mode register 0: r55 1: buz (buzzer port) address: ca h reset value: undefined - t1s - ec0s - - int1s int0 s pmr4 address: d0 h reset value: -0-0--00 0: r41 1: int1 0: r46 1: t1o 0: r44 1: ec0 0: r40 1: int0 - - - - ieds address: f8 h reset value: ----0000 edge selection register external interrupt edge select 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) int1 int0 port 4 mode register msb lsb msb lsb lsb hyundai microelectronics GMS81504 23
r6 and r6dd registers: r6 is a 4-bit port (address cc h ). pins r64~r67 are individually configurable as input and output through the r6dd register (address cd h ). port pin alternate function r64 r65 r66 r67 an4 (adc input 4) an5 (adc input 5) an6 (adc input 6) an7 (adc input 7) r6dd (address cd h ) controls the direction of the r6 pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. r67 r66 r65 r64 - - - - port 6 data register address: cc h reset value: undefined r67 r66 r65 r64 - - - - r6dd address: cd h reset value: 0000---- direction select 0: input 1: output input/ output data r6 port 6 direction register GMS81504 hyundai microelectronics 24
basic interval timer the GMS81504 has one 8-bit basic interval timer that is free-run, can not stop. block diagram is shown in figure 11. the 8-bit basic interval timer register (bitr) is incre - mented every internal count pulse which is divided by prescaler. since prescaler has divided ratio by 16 to 2048, the count rate is 1/16 to 1/2048 of the oscillator frequency. as the count overflows from ff h to 00 h , this overflow causes to generate the basic interval timer interrupt. the bitr is interrupt request flag of basic interval timer. caution: all control bits of basic interval timer are in ckctlr register which is located at same ad - dress with bitr (address d3 h ). address d3 h is read as bitr, written to ckctlr. when write "1" to bit btcl of ckctlr, data register is cleared to "0" and restart to count-up. it becomes "0" after one machine cycle by hardware. ? 16 ? 32 ? 64 ? 128 ? 256 ? 512 ? 1024 ? 2048 bitr (8 bits) basic interval timer interrupt btcl bitif bts[2:0] clear x in pin prescaler mux 3 8 figure 11. block diagram of the basic interval timer symbol position name and significance enpck ckctlr.4 enable peripheral clock. 1: supply clock to every peripherals 0: stop clock btcl ckctlr.3 btcl is set to "1", bitr is cleared. btcl becomes "0" automatically after one machine cycle, and starts counting. basic interval timer clock selection bts2 bts1 bts0 prescale value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 32 64 128 256 512 1024 2048 - - enpck btcl bts1 bts2 bts0 - ckctlr address: d3 h reset value: ---10111 figure 12. ckctlr: control clock register hyundai microelectronics GMS81504 25
timer/counter the GMS81504 has two timer/counter registers. each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). timer 0 and timer 1 are can be used either the two 8-bit timer/counter or one 16-bit timer/counter to combine them. in the "timer" function, the register is incremented every internal clock input. thus, one can think of it as counting internal clock input. since a least clock con - sists of 4 and most clock consists of 64 oscillator periods, the count rate is 1/4 to 1/64 of the oscillator frequency. in the "counter" function, the register is incremented in response to a 1-to-0 (falling edge) transition at its corresponding external input pin, ec0 . in addition the "capture" function, the register is incre - mented in response external or internal clock sources same with timer or counter function. when external clock edge input, the count register is captured into timer data register correspondingly. it has four operating modes: "8-bit timer/counter", "16-bit timer/counter", "8-bit capture", "16-bit cap - ture" which are selected by bit in timer mode register tm0 as shown in right table. tm0 for timer 0, timer 1 cap 0 t1sl1 t1sl0 timer 0 timer 1 0 0 0 16-bit timer/counter 1 0 0 16-bit capture 0 x x 8-bit timer 8-bit timer 1 x x 8-bit capture 8-bit timer tdr0 match (tdr0 = t0) 00 h timer 0 interrupt tim e clear clear occur interrupt clear occur interrupt f2 f3 f4 f6 interrupt period occur interrupt 1 2 3 f1 count pulse period when tm0: 00110111 (prescaler= 16) tdr0: fa h = 250 d oscillator freq.= 4mhz interrupt period = 1 4 10 6 hz 16 250 = 1ms f7 f8 f9 fa f5 ex) 4 us figure 13. timer count operation example GMS81504 hyundai microelectronics 26
tdr0 match 00 h timer interrupt tim e clear clear clear occur interrup t occur interrupt match clear and start stop stop txst txcn restart count up high low high low figure 14. timer count operation hyundai microelectronics GMS81504 27
8-bit timer/counter mode the GMS81504 has two 8-bit timer/counters, timer 0, timer 1. the timer 0, timer 1 only as shown in figure 15. the "timer" or "counter" function is selected by control registers tm0 as shown in figure 17. to use as an 8-bit timer/counter mode, bit cap0 of tm0 should be cleared to "0" and bits t1sl1, t1sl0 of tm0 should not set to zero (figure 15). these timers have each 8-bit count register and data register. the count register is incremented by every internal or external clock input. the internal clock has a prescaler divide ratio option of 4, 16, 64 (selected by control bits t1sl1, t1sl0 of register tm0). in the timer 0, timer register t0 increments from 00 h until it matches tdr0 and then reset to 00 h . the match output of timer 0 generates timer 0 interrupt (latched in t0if bit) as tdrx and tx register are in same address, when reading it as a tx, written to tdrx. caution: the contents of timer data register tdrx should be initialized 1 h ~ff h except 0 h , because it is un - defined after reset. in counter function, the counter is incremented every 1-to-0 (falling edge) transition of ec0 pin. in order to use counter function, the bit ec0s of the port mode register pmr4 are set to "1". the timer 0 can be used as a counter by pin ec0 input, but timer 1 can not. tm 0 cap0 t1st t1sl 1 t1sl0 t0st t0cn t0sl 1 t0sl0 0 x 1 0 1 0 x x x x ? 4 ? 16 ? 64 tdr0 (8-bits) timer 0 interrupt t0sl[1:0] x in pin ec0 pin t0 (8-bits) t0cn comparator t0st clear timer 1 interrupt t1o pin t1if f/f t0if mux t1sl[1:0] mux tdr1 (8-bits) t1 (8-bits) t1st prescaler comparator clear timer 0 timer 1 msb lsb edge detector 0: stop 1: clear and start 0: stop 1: clear and start address: e2 h reset value: 00 h "1" "0" figure 15. 8-bit timer/counter mode GMS81504 hyundai microelectronics 28
to pulse out, the timer match can goes to port pin as shown in figure 15. thus, pulse out is generated by the timer match. these operation is implemented to pin t1o. the pin t1o is output from timer 1. output frequency is calculated as following equation. f t 1 o ( hz ) = f xin 2 prescaler tdr f t1o : pin t1o output pulse frequency f xin : oscillator frequency prescaler: refer to bit t1sl1,t1sl0 of tm0 at figure 17. lsb msb - t1s ec0s - int1s - int0s - pmr4 address: d0 h reset value: -0-0--00 0: r40 1: int0 (external interrupt 0) 0: r41 1: int1 (external interrupt 1) 0: r44 1: ec0 (external input pin for timer 0) 0: r46 1: t1o (timer 1 pulse output) figure 16. pmr4: r4 port mode register timer 1 timer 0 t1sl1 t1sl 0 input clock t0sl1 t0sl 0 input clock 0 0 1 1 0 1 0 1 16-bit timer mode (note 1) 8-bit timer, ? 4 ? prescaler 8-bit timer, ? 16 8-bit timer, ? 64 0 0 1 1 0 1 0 1 timer or counter select ? 4 ? prescaler ? 16 ? 64 tm0 lsb msb t1sl1 t1st t1sl0 t0st t0sl1 t0cn t0sl0 cap0 capture mode selection flag, when set, timer operate as one 16-bit capture timer combine two 8-bit timers. cap0 when set, timer 1 count register is cleared and start again. when cleared, stop the counting. t1st start/stop control for timer 0. a logic 1 starts the timer. t0cn when set, the timer 0 count register is cleared and start again. when cleared, stop the counting. t0st timer 1 timer 0 note: if this mode selected, the timer 0 are used as a 16-bit timer mode. the timer 1 is engaged to the ti mer 0. the source clock is selected by bits t0sl1 and t0sl0. address: e2 h reset value: 00h figure 17. tm0: timer 0, timer 1 mode register hyundai microelectronics GMS81504 29
16-bit timer/counter mode the timer register is being run with all 16 bits. a 16-bit timer/counter register t0, t1 are incremented from 0000 h until it matches tdr0, tdr1 and then resets to 0000 h . the match output generates timer 0 inter - rupt. the clock source of the timer 0 is selected either internal or external clock by bit t0sl1, t0sl0. bit t1st is not effect in this 16-bit mode. bit t0sl1 and t0sl0 select the clock source among three prescaler divide ratio and external ec0 clock. tm 0 cap0 t1st t1sl 1 t1sl0 t0st t0cn t0sl 1 t0sl0 0 x 0 0 x x x x msb lsb ? 4 ? 16 ? 64 tdr0 timer 0 interrupt t0sl[1:0] xin pin ec0 pin t0 t0cn comparator t0st clear t0if mux prescaler timer 0 + timer 1 tdr1 t1 (not timer 1 interrupt) edge detector 0: stop 1: clear and start address: e2 h reset value: 00 h higher lower "1" "0" (16 bits) (16 bits) do not care figure 18. 16-bit timer/counter mode GMS81504 hyundai microelectronics 30
8-bit capture mode the timer 0 capture mode is set by bit cap0 of timer mode register tm0 as shown in figure 19. in this mode, timer 1 still operates as an 8-bit timer/counter. in 8-bit capture mode, timer 1 can not be used as capture mode. the timer/counter register is incremented in response internal or external input. this counting function is same with normal timer mode, but timer interrupt is not generated. timer/counter still does the above, but with the added feature that a edge transition at external input int0 pin causes the current value in the timer 0 register t0, to be captured into registers cdr0, respec - tively. after captured, timer 0 register t0 is cleared and restarts by hardware. caution: the cdrx and tdrx are in same address. in the capture mode, reading operation is read the cdrx, not tdrx because path is opened to the cdrx. it has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register ieds (refer to external inter - rupt section). in addition, the transition at int0 pin generates an interrupt signal. tm0 cap0 t1st t1sl1 t1sl0 t0st t0cn t0sl1 t0sl0 1 x 1 0 1 0 x x x x ? 4 ? 16 ? 64 t0sl[1:0] xin pin ec0 pin t0 (8-bits) t0cn t0st mux int0 pin cdr0 (8-bits) int0 interrupt int0if ieds[1:0] edge detector prescaler msb lsb 0: stop 1: clear and start capture address: e2 h reset value: 00 h 1 0 timer 1 interrupt t1o pin t1if f/f tdr1 (8-bits) t1 (8-bits) comparator t1sl[1:0] 1 00 t1st clear 0: stop 1: clear and start mux timer 0 timer 1 figure 19. 8-bit capture mode hyundai microelectronics GMS81504 31
16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is being run will 16 bits. bit t1st is not effect in this 16-bit mode. bit t0sl1 and t0sl0 select the clock source among three prescaler divide ratio and external ec0 clock. tm0 cap0 t1st t1sl1 t1sl0 t0st t0cn t0sl1 t0sl0 1 x 0 0 x x x x msb lsb ? 4 ? 16 ? 64 t0sl[1:0] xin pin ec0 pin t1 (8-bits) t0cn t0st mux int0 pin cdr1 (8-bits) int 0 interrupt int0if ieds[1:0] t0 (8-bits) cdr0 (8-bits) prescaler edge detector timer 0 + timer 1 address: e2 h reset value: 00 h 0: stop 1: clear and start higher lower 1 0 do not care figure 20. 16-bit capture mode GMS81504 hyundai microelectronics 32
analog to digital converter the analog-to-digital converter (a/d) allows conver - sion of an analog input signal to a corresponding 8-bit digital value. the a/d module has eight analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog supply voltage is con - nected to av dd of ladder resistance of a/d module. the a/d module has two registers which are the con - trol register adcm and a/d result register adr. the register adcm, shown in figure 22, controls the operation of the a/d converter module. the port pins can be configured as analog inputs or digital i/o. to use analog inputs, i/o is selected input mode by r6dd direction register. how to use a/d converter the processing of conversion is start when the start bit adst is set to "1". after one cycle, it is cleared by hardware. the register adr contains the results of the a/d conversion. when the conversion is completed, the result is loaded into the adr, the a/d conversion status bit adsf is set to "1", and the a/d interrupt flag aif is set. the block diagram of the a/d module is shown in figure 21. the a/d status bit adsf is set automatically when a/d conversion is completed, cleared when a/d conversion is in process. the con - version time takes maximum 40 us (at f xin =4 mhz). r65/an5 av dd pin r64/an4 r67/an7 r66/an6 adr a/d interrupt s/h ads[2:0] v in 101 110 111 input channel selection a/d result register 3 address: e9 h reset value: undefined aif sample & hold ladder resistor decoder aden "0" "1" successive approximation circuit 000~011: reserved 100 figure 21. a/d block diagram hyundai microelectronics GMS81504 33
r - aden - ads2 ads1 adst ads0 adsf - adcm a/d status bit (read only) 0: a/d conversion is in process. 1: a/d conversion is completed, not in process. a/d start bit 1: setting this bit starts an a/d conversion. after one cycle, bit is cleared to "0". 0: bit force to zero. analog channel select 000~011: reserved 100: channel 4 (r64/an4) 101: channel 5 (r65/an5) 110: channel 6 (r66/an6) 111: channel 7 (r67/an7) a/d converter enable bit 0: a/d converter module shut off and consumes no operating current. 1: enable a/d converter reserved address: e8 h reset value: --00001 lsb msb r/w r/w r/w r/w r/w - figure 22. adcm: a/d converter control register GMS81504 hyundai microelectronics 34
buzzer function the buzzer driver consists of 6-bit binary counter, the buzzer register bur and the clock selector. it gener - ates square-wave which is very wide range frequency (250 hz~125 khz at f xin =4 mhz) by user program - mable counter. pin r55 is assigned for output port of buzzer driver by setting the bit 5 of pmr5 (address d1 h ) to "1". at this time, the pin r55 must be defined as output mode (the bit 5 of r5dd=1). in the emulator, even if pin r55 is defined as input, buzzer output is available. the bit 0 to 5 of bur determines output frequency for buzzer sound. frequency calculation is following below. f bu z ( h z ) = f xin 2 prescaler ratio bu r value f buz : buzzer frequency f xin : oscillator frequency prescaler: prescaler divide ratio by buck1, buck0 bur:lower 6-bit of bur. buzzer period data value the bits buck1, buck0 of bur selects the source clock from prescaler output. the 6-bit buzzer counter is cleared and start the count - ing by writing signal to the register bur. it is incre - ment from 00 h until it matches 6-bit register bur. caution: the register bur contains undefined value after reset. it must be initialized with 1 h ~3f h (none 0 h ). ? 16 ? 32 ? 64 ? 128 counter (6 bit) bur[5:0] (6 bit) mux bur[7:6] f/f x in pin prescaler bur register buz pin figure 23. buzzer driver lsb msb bu5 buck0 bu4 bu3 bu1 bu2 bu0 buck 1 bur address: ec h reset value: undefined prescaler ratio 00: fx in ? 16 01: fx in ? 32 10: fx in ? 64 11: fx in ? 128 6-bit bur value figure 24. bur: buzzer period data register lsb msb buzs - - - - - - - pmr5 address: d1 h reset value: --0----- r55/ buz port selection 0: r55 1: buz figure 25. pmr5: port 5 mode register hyundai microelectronics GMS81504 35
interrupts the GMS81504 interrupt circuits consist of interrupt enable register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit and master enable flag(i flag of psw). the configuration of interrupt circuit is shown in figure 1- 26. 12 interrupt sources are provided including the reset. interrupt source symbol priority hardware reset external interrupt 0 external interrupt 1 timer/counter 0 timer/counter 1 ad converter basic interval timer reset int0if int1if t0if t1if aif bitif 1 2 3 4 5 6 7 *vector addresses are shown in program memory section. the external interrupts int0, int1 can each be tran - sition-activated, depending on interrupt edge selection register. the timer 0, timer 1 interrupts are generated by t0if, t1if, which are set by a match in their respective timer/counter register. the ad converter interrupt is generated by aif which is set by finishing the analog to digital conversion. the basic interval timer interrupt is generated by bitif which are set by a overflow in the timer/counter register. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw), the interrupt enable register (ienh, ienl) and the interrupt request flags (in irqh, irql) except power-on reset and software brk interrupt. interrupt enable registers are shown in figure 27. these registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. when enable flag is "0", a corresponding interrupt source is prohibited. note that psw contains also a master en - able bit, i-flag, which disables all interrupts at once. int0if int1if t0if t1if aif bitif priority control timer0 reset brk (software interrupt) i-flag master interrupt enable flag 1 0 i-flag is in psw, it is cleared by "di", set by "ei" instruction. when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by "reti" instruction, i-flag is set to "1" by hardware. ienh ienl irqh irql int1 int0 timer1 adc note: * bit: basic interval timer to cpu bit 7 bit 5 release the stop (if in stop mode) 0 1 bit 7 bit 6 bit 3 bit 2 interrupt request flag interrupt enable flag bit * figure 1-26. block diagram of interrupt function GMS81504 hyundai microelectronics 36
when an interrupt is responded to, the i-flag is cleared to disable any further interrupt, the return address is pushed into the stack and the pc is vectored to. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before reenabling interrupts to avoid recursive inter - rupts. the interrupt request flags are able to be read and write. external interrupt external interrupt on int0, int1 pins are edge trig - gered depending on the edge selection register ieds. the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, both edge. int0, int1 are multiplexed with general i/o ports (r40, r41). to use external interrupt pin, set bit 0 to bit 3 of the port mode register pmr4. the pmr4 and ieds registers are shown in figure 30. msb lsb lsb msb - int1e - t0e - t1e - int0 e ienh enables or disables the interrupt individually. if flag is cleared, the interrupt is disabled. 0: disable 1: enable bite - - - - - - a e ienl address: f6 h reset value: 00--00-- address: f4 h reset value: 0-0----- figure 27. ienh, ienl: interrupt enable registers int0 int0 interrupt ieds[1:0] edge detector int0if int1 int1 interrupt ieds[3:2] int1if figure 28. external interrupt hyundai microelectronics GMS81504 37
interrupt active f xin 8 f osc max. 13 f osc instruction execution (interrupt holding) interrupt processing interrupt routine figure 29. int pin interrupt timing lsb msb - - - ied1h ied0h ied1l ied0l - ieds address: f8 h reset value: ----0000 int1 int0 edge selection register iedxh.iedxl 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) lsb msb - t1s ec0s - int1s - int0s - pmr4 address: d0 h reset value: -0-0--00 0: r40 1: int0 (external interrupt 0) 0: r41 1: int0 (external interrupt 1) 0: r44 1: ec0 (external input pin for timer 0) 0: r46 1: t1o (timer 1 pulse output) figure 30. pmr4 and ieds registers GMS81504 hyundai microelectronics 38
brk interrupt software interrupt can be invoked by brk instruction, which is the lowest priority order. interrupt vector address of brk is shared with the vector of tcall0 (refer to program memory sec - tion). when brk interrupt is generated, b-flag of psw is set to distinguish brk from tcall0. each processing step is determined by b-flag as shown below. multiple interrupt if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. hardware interrupt priority is shown in page 36. however, multiple processing through software for special features is possible. generally when an inter - rupt is accepted, the i-flag is cleared to disable any further interrupt. but as user set i-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. b-flag reti brk or tcall0 brk interrupt routine tcall0 routine ret = 0 = 1 figure 31. execution of brk/ tcall0 mov ienh,#80h mov ienl,#00h ei reti occur timer 0 interrupt int0 routine reti main routine timer 0 routine mov ienh,#ffh mov ienl,#ffh int 0 routine in this example, the int0 interrupt can be serviced without any pending, even timer 0 is in progress. because of re-setting the interrupt enable registers ienh, ienl and master enable flag "ei" in the timer/counter 0 routine. figure 32. execution of multi-interrupt hyundai microelectronics GMS81504 39
stop mode for applications where power consumption is a critical factor, device provides reduced power of stop. an instruction that stop causes that to be the last instruction executed before going into the stop mode. in the stop mode, the on-chip oscillator is stopped. with the clock frozen, all functions are stopped, but the on-chip ram and control registers are held. the port pins out the values held by their respective port data register rx, port direction register rxdd. the status of peripherals during stop mode is shown below. peripheral status ram retain control registers retain i/o retain oscillation stop x in low x out high in the stop mode of operation, v dd can be reduced to minimize power consumption. care must be taken, however, to ensure that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level, before the stop mode is termi - nated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize (minimum 20 msec). caution: the nop instruction have to be written more than two to next line of the stop instruction. ex) stop nop nop release stop mode the exit from stop mode is hardware reset or external interrupt. reset redefines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. if i-flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vector to interrupt service routine. when exit from stop mode by external interrupt from stop mode, enough oscillation stabilization time is required to normal operation. figure 33 shows the timing diagram. when release the stop mode, the external interrupt internal clock oscillator t st > 20 ms normal operation basic interval timer counter clear basic interval timer n+2 00 01 fe ff 0 0 n n+1 stabilization time 01 02 03 normal operation stop mode stop instruction execution figure 33. timing of stop release by external interrupt GMS81504 hyundai microelectronics 40
basic interval timer is activated on wake-up. it is incremented from 00 h until ff h then 00 h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant prescaler divide ratio to have long enough time. this guarantees that crystal oscillator has started and stabi - lized. by reset, exit from stop mode is shown in figure 34. minimizing current consumption in stop mode the stop mode is designed to reduce power consump - tion. to minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. weak pull-ups on port pins should be turned off, if possible. all inputs should be either as v ss or at v dd (or as close to rail as possible). an intermediate voltage on an input pin causes the input buffer to draw a significant amount of current. stop mode reset internal clock oscillator stop instruction execution t st = 64 ms at 8 mhz stabilization time time can not be control by software. figure 34. timing of stop mode release by reset wake-up and reset function table event chip status before event chip function after event pc oscillator circuit reset do not care vector on stop instruction normal operation n+1 off external interrupt normal operation vector on external interrupt wake-up stop, i-flag = 1 stop, i-flag = 0 vector n+1 on on pc: program counter contents after the event. n: address of stop instruction. hyundai microelectronics GMS81504 41
reset the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, while the oscillator running. after reset, 64ms (at 8 mhz) plus 7 oscillator periods are required to start execution as shown in figure 36. internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. initial state of each register is as follow. therefore, this ram should be initialized before reading or testing it. register content a x y psw pc sp x x x 00h x x r0 r0dd r4 r4dd r5 r5dd r6 r6dd pmr4 pmr5 x 00000000 x 00000000 x 000----- x 0000---- -0-0--00 --0----- bitr ckctlr tm0 tdr0/ t0/ cdr0 tdr1/ t1/ cdr1 00h --010111 00h x x adcm adr bur --000001 x x ienh ienl irqh irql ieds 00--00-- 0-0----- 00--00-- 0-0----- -----000 - = unimplemented bit x= unknown reset +5v 4.2v reset ic 7042 10k w 10uf + 4.2v reset ic ex) 5v operation figure 35. example of reset circuit reset oscillator 1 2 3 4 5 6 7 ? ? ? ? ? fff e ffff start reset process step address bus ? ? data bus ? ? fe adl adh op code main program t st = 64 ms at 8 mhz stabilization time figure 36. timing diagram after reset GMS81504 hyundai microelectronics 42
oscillator circuit x in and x out are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 37. to drive the device from an external clock source, x out should be left unconnected while x in is driven as shown in figure 39. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crys - tal and ceramic resonator have their own charac - teristics, the user should consult the crystal manufacturer for appropriate values of external com - ponents. in addition, see figure 38. for the layout of the crystal. in all cases, an external clock operation is available. x out x in v ss recommend: c1,c2 = 30 pf 10 pf for crystals. c1 c2 figure 37. oscillator connections v ss x in x out reset r00 r01 figure 38. layout of crystal x out x in v ss n/c external oscillator signal figure 39. external clock drive configuration hyundai microelectronics GMS81504 43
otp programming the GMS81504t is one-time prom (otp) micro - controller with 4k bytes electrically programmable read only memory for the GMS81504 system evalu - ation, first production and fast mass production. to programming the otp device, user can have two way. one is using the universal programmer which is support hme microcontrollers, other is using the gen - eral eprom programmer. 1. using the universal programmer third party universal programmer are shown as below. manufacturer: advantech web site: http://www.aec.com.tw programmer: labtool-48 manufacturer: hi-lo systems web site: http://www.hilosystems.com.tw programmer: all-11, gang-08 socket adapters are supported from third party pro - grammer manufacturer. 2. using the general eprom(27c256) programmer when user use general eprom programmer, socket adaper is essencially necessary. it convert pin to fit the pin of general 27c256 eprom. socket adapter: oa815a-30sd (30sdip) in assembler and file type, two files are generated after compiled. one is "*.hex", another is "*.otp". the "*.hex" file is used for emulation in circuit emulator choice-jr tm and "*.otp" file is used for program - ming to otp device. programming procedure 1. select the eprom device and manufacturer on eprom programmer (intel 27c256) 2. select the programming algorithm as a intelligent mode (apply 1ms writing pulse). 3. load the file (*.otp) to the programmer. 4. set the programming address range as below table. address set value buffer start address 7000 h buffer end address 7fff h device start address 7000 h 5. mount the socket adapter with the otp device onto the prom programmer. 6. start the prom programmer to programming/ verifying. GMS81504 hyundai microelectronics 44
GMS81504t programming manual
device overview the GMS81504t is a high-performance cmos 8-bit microcontroller with 4k bytes of eprom. the de v ice is one of gms800 family. the hyundai GMS81504t is a powerful microcontroller which provide s a highly flexible and cost effective solution to many embedded control applications. the GMS81504 t provides the following standard features: 4k bytes of eprom, 128 bytes of ram, 23 i/o lines, 16-bit or 8-bi t timer/counter, a precision analog to digital converter, on-chip oscillator and clock circuitry. pin description notes: 1. check marked pins must be connected on v ss , because these pins are input ports during programming, program verify and reading 2. x out pin must be opened during programming. pin no. mcu mode otp mode 1 r01 i/o o1 i/o 2 r00 i/o o0 i/o 3 r47 i/o a0 i 4 r46 i/o a1 i 5 r45 i/o ce i 6 r44 i/o oe i 7 r67/an7 i/o a2 i 8 r66/an6 i/o a3 i 9 av ref i (1) i 10 r65/an5 i/o a4 i 11 r64/an4 i/o (1) i 12 r41/int1 i/o a5 i 13 r40/int0 i/o a6 i 14 r55/buz i/o a7 i 15 r56 i/o a8 i pin no. mcu mode otp mode 16 r57 i/o a9 i 17 reset i (1) i 18 x in i (1) i 19 x out o (2) o 20 v ss v ss v ss v ss 21 r43 i/o a10 i 22 r42 i/o a11 i 23 test i/o v pp v pp 24 r07 i/o o7 i/o 25 r06 i/o o6 i/o 26 r05 i/o o5 i/o 27 r04 i/o o4 i/o 28 r03 i/o o3 i/o 29 r02 i/o o2 i/o 30 v dd v dd v dd v dd i/o: input/output pin i: input pin o: output pin h yu nd ai m ic ro e le c t ro nic s GMS81504t programming specification 1
pin function (otp mode) v pp (program voltage) v pp is the input for the program voltage for program - ming the eprom. ce ( chip enable) ce is the input for programming and verifying inter - nal eprom. oe (output enable) oe is the input of data output control signal for verify. a 0 ~a 11 (address bus) a 0 ~a 11 are address input pins for internal eprom. o 0 ~o 7 (eprom data bus) these are data bus for internal eprom. programming the GMS81504t has address a 0 ~a 11 pins. therefore, the programmer just program 4k bytes data (address 7000 h to 7fff h ) into the GMS81504t otp device. during the programming, addresses a 12 ~a 15 of the programmer must be pulled to a logic high. when the programmer write the data from 7000 h to 7fff h , consequently, the data actually will be written into addresses f000 h to ffff h of the otp device. 1. the data format to be programmed is made up of motorola s1 format. ex) "motorola s1" format; s0080000574154434880 s1247000e1ff3bff04a13f8f06e101711b821b1be01d1b3b191bf6181bf01c1bff081bff0ab0 s12470211bf5091bff0b1bff3f1b003e1b003d1b003c1bff3b1b003a1bff391bff381bff350d : : s1057ff2983fb2 s1057ffeff0f6f s9030000fc 2. down load above data into programmer from pc. 3. programming the data from address 7000 h to 7fff h into otp mcu, the data must be turned over respectively, and then record the data.when read the data, it also must be turned over. ex) 00(00000000) ? ff(11111111), 76(01110110) ? 89(10001001), ff (11111111)? 00(00000000) etc. 4. of course, the check sum is result of the sum of whole data from address 7000 h to 7fff h in the file (not reverse pin connection during programming GMS81504t programming specification hyundai microelectronics 2
data of theotp mcu). * when GMS81504t shipped, the blank data of it is initially 00 h (not ff h ). address GMS81504t device file xxxxxxxx.otp e1 ff 3b ff 04 a1 3f 8f : : : : 98 3f : ff 0f down loadin g program 7000 h 7001 h 7002 h 7003 h 7004 h 7005 h 7006 h 7007 h : : : : 7ff2 h 7ff3 h : 7ffe h 7fff h e1 ff 3b ff 04 a1 3f 8f : : : : 98 3f : ff 0f 7000 h 7001 h 7002 h 7003 h 7004 h 7005 h 7006 h 7007 h : : : : 7ff2 h 7ff3 h : 7ffe h 7fff h 1e 00 c4 00 fc 5e c0 70 : : : : 67 c0 : 00 f0 f000 h f001 h f002 h f003 h f004 h f005 h f006 h f007 h : : : : fff2 h fff3 h : fffe h ffff h reading verify up loading data addres s data addres s data programmer buffer checksum = e1+ff+3b+ff+04+a1+3f+8f+ + 98+3f+ +ff+0f programming example program area 4 k bytes f000 h ffff h address file type: motorola s-format GMS81504t 7000 h 7fff h address xxxxxxxx.otp universal programmer down loading program verify reading buffer start address:7000 h buffer end address: 7fff h device start address: f000 h programming flow hyundai microelectronics GMS81504t programming specification 3
device operation mode (t a = 25 c 5 c) mode ce oe a 0 ~a 11 v pp v dd o 0 ~o 7 read x x v dd 5.0v d out output disable v ih v ih x v dd 5.0v hi-z programming v il v ih x v pp v dd d in program verify x x v pp v dd d out notes: 1. x = either v il or v ih 2. see dc characteristics table for v dd and v pp voltages during programming. dc characteristics (v ss =0 v, t a = 25 c 5 c) symbol item min typ max unit test condition v pp intelligent programming 12.0 - 13.0 v quick-pulse programming 12.5 - 13.0 v v dd (1) intelligent programming 5.75 - 6.25 v quick-pulse programming 6.0 - 6.5 v i pp (2) v pp supply current 50 ma ce =v il i dd (2) v dd supply current 30 ma v ih input high voltage 0.8 v dd v v il input low voltage 0.2 v dd v v oh output high voltage v dd -1.0 v i oh = -2.5 ma v ol output low voltage 0.4 v i ol = 2.1 ma i il input leakage current 5 ua notes: 1. v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. the maximum current value is with outputs o 0 to o 7 unloaded. GMS81504t programming specification hyundai microelectronics 4
notes: 1. the input timing reference level is 1.0 v for a v il and 4.0v for a v ih at v dd =5.0v 2. to read the output data, transition requires on the oe from the high to the low after address setup time t as . address valid t oe valid output t dh addresses oe output high-z v ih v il v ih v il v ih v il t as (2) reading waveforms waveform inputs outputs must be steady may change from h to l may change from l to h do not care any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high impedance "off" state switching waveforms hyundai microelectronics GMS81504t programming specification 5
notes: 1. the input timing reference level is 1.0 v for a v il and 4.0v for a v ih at v dd =5.0v t dfp addresses data high-z v ih v il 12.5v v dd v pp v dd ce oe 6.0v 5.0v t as t ds t vps t vds t opw t pw t oes program program verify t dh v ih v il v ih v il v ih v il t ah address stable data in stable data out valid t oe programming algorithm waveforms GMS81504t programming specification hyundai microelectronics 6
ac reading characteristics (v ss =0 v, t a = 25 c 5 c) symbol item min typ max unit test condition t as address setup time 2 us t oe data output delay time 200 ns t dh data hold time 0 ns notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . ac programming characteristics (v ss =0 v, t a = 25 c 5 c; see dc characteristics table for v dd and v pp voltages.) symbol item min typ max unit condition* (note 1) t as address set-up time 2 us t oes oe set-up time 2 us t ds data setup time 2 us t ah address hold time 0 us t dh data hold time 1 us t dfp output disable delay time 0 us t vps v pp setup time 2 us t vds v dd setup time 2 us t pw program pulse width 0.95 1.0 1.05 ms t opw ce pulse width when over programming 2.85 78.75 ms (note 2) t oe data output delay time 200 ns *ac conditions of test input rise and fall times (10% to 90%) . . . . 20 ns input pulse levels . . . . . . . . . . . . . . . 0.45v to 4.55v input timing reference level . . . . . . . . . 1.0v to 4.0v output timing reference level . . . . . . . . 1.0v to 4.0v notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. the length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value x (intelligent programming algorithm only). refer to page 8 . hyundai microelectronics GMS81504t programming specification 7
start address= first location v cc = 6.0v v pp = 12.5v x = 0 program one 1 ms pulse increment x x = 25 ? verify byte verify one byte last address ? v cc = v pp = 5.0v compare all bytes to original data device passed increment address yes no fail pass fail pass no yes fail pass device failed program one pulse of 3x msec duration intelligent programming algorithm GMS81504t programming specification hyundai microelectronics 8
mask order & verification sheet GMS81504-hb 1. customer information company name 2. device information 3. marking specification 4. delivery schedule customer sample date yyyy mm dd risk order yyyy mm dd quantity hme confirmation application order date yyyy mm dd te l : fax: name & signature: package hme 5. rom code verification verification date: yyyy mm dd approval date: yyyy mm dd please confirm our verification data. i agree with your verification data and confirm you to make mask set. check sum: te l : fax: name & signature: te l : fax: name & signature: set ff h in this area 0000 h 7fff h .otp file data file name (please check mark into ) hyundai microelectronics pcs pcs check sum customer should write inside thick line box. this box is written after 5.verification. hitel 30sdip 28sop chollian mask data internet 27256 .otp ( ) 7000 h ( 4k ) yyww korea GMS81504-hbxxx yyww korea GMS81504-hbxxx customers logo customer logo is not required customers part number note: if the customer logo must be used in the special mark please submit a clean original of the logo. 6fff h hme rom code number

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